Photolithography or optical lithography systems used in the manufacture of integrated circuits have been around for some time. Such systems have proven extremely effective in the precise manufacturing and formation of very small details in the product. In some photolithography systems, a circuit image is written on a substrate by transferring a pattern via a light or radiation beam (e.g., UV or ultraviolet light). For example, the lithography system may include a light or radiation source that projects a circuit image through a reticle and onto a silicon wafer coated with a material sensitive to irradiation, e.g., photoresist. The exposed photoresist typically forms a pattern that after development masks the layers of the wafer during subsequent processing steps, as for example deposition and/or etching.
Due to the large scale of circuit integration and the decreasing size of semiconductor devices, the reticles and fabricated devices have become increasingly sensitive to critical dimension (CD) variations, as well as other critical parameter variations such as film thickness and composition, etc. These variations, if uncorrected, can cause the final device to fail to meet the desired performance due to electrical timing errors. Even worse, these errors can cause final devices to malfunction and adversely affect yield.
In one metrology technique, critical dimension is measured by scanning electron microscope CD-SEM images at each target location on the wafer and examining each image for pattern quality. This technique is time consuming (e.g., several hours). Other techniques have their own disadvantages.
Additionally, buried defects can be difficult to detect with certain metrology tools. Traditionally, the only way to know the size, distribution and location of buried voids, for example, is by using destructive methods such as Focused Ion Beam (FIB) cross-sectioning techniques. Although these techniques can help verify the existence of voids, the sample is destroyed during the analysis. This technique is expensive for integrated circuit manufacturers since it means sacrificing product samples from the product line and often results in wasting product found to have no significant defects. Furthermore, FIB techniques are time consuming, which can cause downtime of the product line production. This increased downtime can be an especially big problem if numerous scans on numerous wafers are needed to ensure void-free processing.
In view of the foregoing, improved apparatus and techniques for determining structure or process parameters of a printed pattern are desired.